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www.fairchildsemi.com ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 an-6067 design and application of primary-side regulation (psr) pwm controller fan100 / fan102 / fsez1016a / FSEZ1216 abstract this application note describes a typical charger using the psr controller. both the features of this controller, as well as the operation of the power supply adaptor, are presented in detail. based on the proposed design guideline, a design example with detailed parameters is given to demonstrate the superior performance of the controller. applications ? battery chargers for cellular phones, cordless phones, pdas, digital cameras, power tools ? optimal choice for the replacement of linear transformers and rcc smps features ? constant-voltage (cv) and constant-current (cc) control without secondary-feedback circuitry ? accurate constant current achieved by fairchild?s proprietary truecurrent ? technique ? green-mode function: pwm frequency decreasing linearly ? fixed pwm frequency at 42khz with frequency hopping to solve emi problems ? low startup current: 10 a (typical) ? low operating current: 3.5ma (typical) ? peak-current-mode control ? cycle-by-cycle current limiting ? v dd over-voltage protection (ovp) ? v dd under-voltage lockout (uvlo) ? gate output maximum voltage clamped at 18v ? fixed over-temperature protection (otp) ? cable compensation for tight cv regulation (fan102 / FSEZ1216) psr pwm controller fan100 psr pwm controller fan102 fan100 + cable compensation fsez1016a fan100 + mosfet (1a/600v) FSEZ1216 fan102 + mosfet (1a/600v) pin configurations figure 1. fan100 figure 2. fan102 figure 3. fsez1016a figure 4. FSEZ1216
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 2 typical applications comi comv sgnd vdd vs cs gate pgnd fan100 1 2 3 4 5 6 7 8 vbus comi comv gnd vdd vs cs gate comr 1 2 3 4 5 6 7 8 figure 5. fan100 figure 6. fan102 (fan100 + cable compensation) comi comv gnd vdd vs cs drain n .c. fsez1016a 1 7 3 4 5 2 6 8 vbus FSEZ1216 vbus comi comv gnd vdd vs cs drain comr 1 2 3 4 5 7 6 8 figure 7. fsez1016a (fan100 + mosfet) figure 8. FSEZ1216 (fan102 + mosefet)
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 3 block diagrams figure 9. fsez1016a (fan100 + mosfet)
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 4 block diagrams (continued) figure 10. FSEZ1216 (fan102 + mosfet)
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 5 introduction this highly integrated psr pwm controller contains several features to enhance the performance of low-power flyback converters. the patented topology of the psr controller allows for simplified of circuit designs, particularly battery charger applications. cv and cc control can be accurately achieved without secondary feedback circuitry. with the addition of frequency-hopping in pwm operation, emi problems can be solved using minimized filter components. as a result, a low-cost, smaller, and lighter charger is produced when compared to a conventional design or a linear transformer. to minimize standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease the pwm frequency under light-load conditions. this green-mode function is designed to help the power supply meet power conservation requirements. the startup current is only 10a, which allows for the use of large startup resistance for further power savings. the psr controller also provides numerous protection functions. the vdd pin is equipped with over-voltage protection and under-voltage lockout. pulse-by-pulse current limiting and cc control ensure over-current protection during heavy loads. the gate output is clamped at 15v to protect the external/internal mosfet from over-voltage damage. additionally, the internal over-temperature- protection function shuts down the controller with auto recovery when over heating occurs. by using the psr controller, a charger can be implemented with few external components and at a minimized cost. internal block operation constant voltage output regulation psr controller?s innovative method can achieve accurate output cv/cc characteristic without voltage and current sensing circuitry on the secondary side. the application circuit and a conceptualized internal block diagram relating to the constant voltage regulation are shown in figure 11, and the key waveform is shown in figure 12. the secondary output status is taken from the primary auxiliary winding when the mosfet is off. a unique sampling method is used to acquire a duplication of the output voltage ( v sah ) and the output diode discharge time ( t dis ). the sampled voltage ( v sah ) is then compared with the precise internal reference voltage ( v ref ) to determine the on-time of the mosfet by modulating error amplifier?s output. this inexpensive method achieves accurate output voltage regulation. vin naux npri nsec vs cs comv / sh p wm vref vsah s i o c o r o v + ? o i 1 r 2 r s r p i :1 n figure 11. internal block of cons tant voltage output operation
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 6 constant current output regulation as shown in figure 12, the output current i o can be expressed by equation 1 when the flyback converter is operated in dcm. as a result, the output current i o can be calculated by the signal i pk , t dis . the psr controller then determines the on-time of the mosfet to modulate input power and provide constant output current. p i s i ts in p v l 2 o - p nv l ? s ampling voltage o i figure 12. principal operation waveform of the flyback converter (dcm) the current-sense resistor can adjust the value of the constant current. through better design of the transformer operations under discontinuous current mode, the psr controller?s proprietary control structure is able to achieve accurate and constant current characteristics. detailed design guideline for the transformer is introduced in the following section. [] [] ? ? ? ? ? ? ? ? ? = ? ? ? = ? ? = dis cs cs p dis pk p pk s dis t r v n ts t i n ts i t ts io 2 1 2 1 2 1 , (1) where: i s,pk is the peak inductor current of the secondary side, i pk is the peak inductor of primary side. t dis is discharge-time of transformer inductor current. n p is the turn ratio between primary and secondary winding. r cs is the current-sense resistor. v cs is the voltage on current-sense resistor. green-mode operation the proprietary green-mode function of the psr controller provides off-time modulation to linearly decrease the pwm frequency at light-load conditions, as low as 500hz. with the green-mode function, the power supply can easily meet the most stringent of power conservation requirements. figure 13 shows the characteristics of the pwm frequency vs. the output voltage of the error amplifier ( v comv ). the psr controller uses the positive, proportional, output load parameter ( v comv ) as an indication of the output load for modulating the pwm frequency. in heavy load conditions, the pwm frequency is fixed at 42khz. once v comv is lower than v n , the pwm frequency starts to linearly decrease from 42khz to 500hz. figure 14 is a measured waveform at burst-mode operation. comv v frequency 1khz g v n v 40khz 42khz 500hz figure 13. pwm frequency vs. v comv figure 14. measured waveform at burst-mode operation vo(ac) 100mv/div gate 10v/div v comv 500mv/div
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 7 frequency hopping operation a frequency hopping function is built in to further improve emi system performance. the frequency hopping period is no longer than 3ms and the pwm switching frequency range is 42khz +/- 2.6khz. +/- 2.6khz 44.6khz frequency hopping period 3ms 39.4khz figure 15. gate signal with frequency hopping cv / cc regulation battery chargers are typically designed for two modes of operation, constant-voltage charging and constant-current charging. the basic charging characteristic is shown in figure 16. when the battery voltage is low, the charger operates on a constant current charging. this is the main method for charging batteries and most of the charging energy is transferred into the batteries. when the battery voltage reaches its end-of-charge voltage, the current begins to taper-off. the charger then enters the constant voltage method of charging. finally, the charging current continues to taper-off until reaching zero. vo(v) io ( ma ) cc regulation cv regulation charging sequence figure 16. basic charging v-i characteristic as mentioned in the cv regulation region section, the v comv modulates mosfet?s on-time and pwm frequency to provide enough power to the output load. as shown in figure 17, as the output load increases, v comv gradually rises until the system shifts into the cc regulation region. at the same time, v comv increases to 4.5v and the moseft?s on time is controlled by v comi . however, when power system operates in the cc regulation region at a fixed 42khz frequency, the mosfet?s on-time is determined by v comi to modulate the output current. cv regulation cc regulation charging sequence 4.5v d eep green mode comv v comi v decreasing output impedance figure 17. cv/cc regulation charging sequence temperature compensation the psr controller has built-in temperature compensation circuitry to provide constant reliable voltage regulation even at a different ambient temperature. this internal positive temperature coefficient (ptc) compensation current is used to compensate for the temperature due to the forward- voltage drop of the diode output. without temperature compensation, the output voltage is distinctly higher in high temperatures than in lower temperature condition, as shown in figure 18. o v o i high temp. room temp. after compensation at high temp. figure 18. output v-i curve with temperature compensation as shown in figure 19, the accuracy value of r1 and r2 determines the voltage regulation amount. the suggested deviation for r1 and r2 is a +/-1% tolerance. auxiliary winding vs temperature compensation ptc psr controller / sh vref figure 19. temperature compensation
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 8 startup circuitry when the power is activated, the input voltage charges the hold-up capacitor (c1) via the startup resistors, as shown in figure 20. as the voltage (v dd ) reaches the startup voltage threshold (v dd-on ), the psr controller activates and drives the entire power supply. dd v gnd psr controller c1 d1 vdc in r d_on t figure 20. single-step circuit connected to the psr controller the power-on delay is determined as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? in st dd ac on dd in on d r i v v c r t 2 1 ln 1 _ (2) where i dd-st is the startup current of the psr controller. due to the low startup current, a large r in value, such as 1.5m can be used. with a hold-up capacitor of 4.7f, the power-on delay t d_on is less than 3s for a 90v ac input. if a shorter startup time is required, a two-step startup circuit, as shown in figure 21, is recommended. in this circuit, a smaller c1 capacito r can be used to decrease startup time without a need for a smaller startup resistor (r in ) and increase the power dissipation on the r in resistor. the energy supporting the psr controller after startup is mainly from a larger capacitor c2. d d v gnd psr controller c1 vdc in r d_on t c2 figure 21. two steps of providing power to the psr controller the maximum power dissipation of r in is: ( ) in dc in dd dc max r r v r v v p in 2 max , 2 max , , ? ? = (3) where v dc,max is the maximum rectified input voltage. take a wide-ranging input (90v ac ~264v ac ) as an example, v dc =100v~380v: mw p max r in 96 10 5 . 1 380 6 2 , ? = (4) built-in slope compensation the sensed voltage across the current sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. within every switching cycle, the psr controller produces a positively sloped, synchronized ramp signal. the built-in slope compensation function improves power supply stability and prevents peak-current-mode control from causing sub-harmonic oscillations. leading edge blanking (leb) each time the mosfet is powered on, a spike, induced by the diode reverse recovery and by the output capacitances of the mosfet and diode, appears on the sensed signal. to avoid premature termination of the moseft, a leading- edge blanking time is introduced in the psr controller. during the blanking period, the current-limit comparator is disabled and unable to switch off the gate driver. under-voltage lockout (uvlo) the power-on and off thresholds of the psr controller are fixed at 16v/5v. during startup, the hold-up capacitor must be charged to 16v through the startup resistor to enable psr controller. the hold-up capacitor continues to supply v dd until power can be delivered from the auxiliary winding of the main transformer (v dd must not drop below 5v during this startup process). this uvlo hysteresis window ensures that the hold-up capacitor can adequately supply v dd during startup. v dd over-voltage protection (ovp) v dd over-voltage protection prevents damage due to over- voltage conditions. when v dd exceeds 28v due to abnormal conditions, pwm output is turned off. over-voltage conditions are usually caused by open feedback loops. over-temperature protection (otp) the psr controller has a built-in temperature sensing circuit to shut down the pwm output if the junction temperature exceeds 145c. when the pwm output shuts down, the v dd voltage gradually drops to the uvlo voltage. some of the internal circuits shut down and v dd gradually starts
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 9 increasing again. when v dd reaches 16v, all the internal circuits, including the temperature sensing circuit, start operating normally. if the junction temperature is still higher than 145c, the pwm controller shuts down immediately. this continues until the temperature drops below 120c. gate output the psr controller bicmos output stage is a fast totem pole gate driver. cross conduction design elimination was used to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 15v zener diode for the protection of power mosfet against over-voltage gate signals. brownout protection the psr controller has a built-in brownout protection circuit to shut down the pwm output. as the input voltage decreases, the flowing current from vs pin is less than i vs- uvp , the pwm output shuts down immediately and enters an auto restart mode. the v dd voltage gradually drops to the uvlo voltage. auxiliary winding vs psr controller vs r mos turns on vs-uvp i figure 22. brownout protection cable compensation the fan102/FSEZ1216 pwm controller has a cable compensation function used to compensate the output voltage drop due to output cable loss. use an external resistor connected from comr pin to gnd adjusts the amount of cable compensation. in cv regulation control, the on-time of mosfet only regulates on-board voltage, not including output cable. different cable wire gauge or length results in different output voltage. as previous mentioned in the cc regulation control section that can calculate the output current. this calculated signal can provide the controller the output load condition and determine the amount of cable compensation, then rescue output voltage drop. to calculate compensation percentage, use the equation below: 6 10 8 . 100 ? = percentage r comr (5) for example, a power board for a charger application is 5v/1a. short the comr pin to gnd first and measure the output voltage from light load to maximum load. if the output voltage with cable is 4.7v at 1a, the percentage to 5v is 6%. calculate the r comr as: ? = ? k r comr 5 . 59 10 8 . 100 6 6 (6) choose the approximate value of r comr and let the output voltage compensate gradually. figure 23 is r comr compared to percentage curve for reference. 0 2 4 6 8 10 12 10 20 30 39 51 60 68 81 91 100 r comr (k ohm) percentage (%) figure 23. r comr vs. percentage lab note before reworking or soldering / desoldering on the power supply, discharge the primary capa citors by way of the external bleeding resistor . if not, the pwm ic may be destroyed by external high-voltage discharge during the soldering / desoldering.
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 10 application information transformer design the transformer inductor current must operate in dcm under any conditions. a typical output v-i curve is shown in figure 24. for discontinuous current mode operation, the transformer inductor should be small enough to meet this condition. point ?b? is the lowest output voltage within the cc regulation and the widest discharge time of the transformer inductor due to the reflected voltage on the primary inductor. it is the easiest into ccm condition for transformer inductor. point ?a? is the maximum output power of the power system. ensure that the magnetic flux density falls within 0.25~0.3 tesla, considered a safe range. the number of turns for primary transformer inductor can be determined on point ?a.? figure 25 shows the characteristic curve of turn ratio and transformer inductance. o v o i ( ) maximum output power determine turn number a b determine primary inductor figure 24. critical operating points to determine the transformer 0 0.5 1 1.5 2 2.5 3 3.5 5 6 7 8 9 10 11 12 13 14 15 n(turn ratio) inductance(mh) b=0.5v b=1v b=1.5v b=2v 1 , 0.45 i oavf v == figure 25. characteristic curve of turn ratio and inductance determine maximum and minimum input voltage figure 26 shows the corrected input voltage waveform. the red line shows ripple voltage on the bulk capacitor and the minimum and maximum voltage on the bulk capacitor is expressed in equations 7 and 8, respectively. the c bulk is the input capacitor and a typical value is 2-3f per watt of output power for wide range input voltage (90-264v). 2.5 assume ms .min in v figure 26. bridge rectifier and bulk capacitor voltage waveform 2 .min ,min 2(1-0.3) 2- 120 oo in ac bulk vi vv c ??? =? ?? (7) .max .max 2 in ac vv =? (8) determine the turn ratio the transformer turn ratio ( n p =n pri /n sec ) is an important parameter of the flyback converter; it affects the maximum duty ratio when the input voltage is at a minimum value. it also influences the voltage stresses on the mosfet and the secondary rectifier. the permissible voltage stresses and the maximum voltage stresses on the mosfet, as well as the secondary rectifier, can be expressed as: .max .max () ds in p o f vvnvv =+?+ (9) .max .max in fo p v vv n = + (10) the leakage spike due to leakage inductance on the mosfet and rectifier must also be taken into account. determine transformer inductance determine the v dd voltage level and if the output voltage is defined. the turn ratio between auxiliary winding and secondary winding can be calculated as: dd fa a of vv n vv + = + (11) where v dd is voltage on v dd cap, usually ranging from about 15v~20v. in the cc regulation region, on point ?b,? the power system shuts down if the output voltage is too low and the v dd
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 11 voltage reaches the turn-off threshold voltage of the psr controller. therefore, if n a was calculated, the vo, ?b? can be obtained as: ," " 6.75 - fa f a ob a vvn v n +? ?? = ?? ?? (12) where: v fa is forward-voltage of rectifier diode of auxiliary winding. v f is forward-voltage of output diode. 6.75v is typically the turn-off threshold voltage of the psr controller. the maximum duty ratio can be calculated by using a point ?b? output condition: ," " .max," " .min," " ," " () () pob f on b in b p o b f nv v d vnvv ?+ = +? + (13) the transformer inductance ( l p ) is designed specifically for dcm operation and a cc tolerance of +/-10% should be considered. the transformer inductance can be obtained as: 22 ," " . min," " max," " ," " 2 bin b b p ob o s vd l vif ?? = ??? (14) where: ,?b? is the estimated system efficiency of point ?b.? if no values are available, use 0.45~0.5 as an initial value. f s is the pwm frequency. after the primary inductance is calculated, the maximum duty ratio of point ?a? can be expressed as: ," " .max," " 2 ," " . min," " 2 oa o p on a ain a s vil d vt ??? = ?? (15) where t s is the switching period. the primary peak inductor current (i pk ) of point ?a? at full load and low line input voltage condition is: .min," " ," " .max," " in a p ka on a s p v idt l =?? (16) determine primary inductance turn number based on faraday?s law and the peak inductor current, the minimum turns for the primary inductance is calculated as: ," " 6 max 10 ppka pri e li n ba ? = ? ? (17) where: b max is the saturation magnetic flux density, a e is the effective area of the core-section. the number of turns for the secondary winding is defined as: sec p ri p n n n = (18) once the secondary winding has been calculated, the number of turns for the auxiliary winding is defined as: sec aux a nnn = ? (19) determine the divider resistor (r 1 ) and current- sense resistor (r s ) once the output voltage v o and auxiliary winding have been defined, the feedback signal divider resistor, r 1 , can be calculated as: () 12 1 a of ref n rr vv v ? ? = ??+? ? ? ? ? ? ? (20) where v ref =2.5v, r 2 is typically set to 15~20k . as discussed in the constant current output regulation section, the region of constant current output operation can be adjusted by the current-sense resistor. after the turn ratio ( n p ) has been determined, the relationship between the output current i o and current sense resistor r s is expressed as: 0.111875 p s o n r i ? = (21) as figure 27 shows, a design spreadsheet can be used to calculate the transformer design and select the power system components for a first prototype. a 5v/1a design example is shown in figure 27.
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 12 figure 27. calculated system parameter by design spreadsheet the parameters in figure 27 can be found in the corresponding components in figure 28. dc v n aux n pri nsec ::1 ap nn vs 1 r 2 r vdd o v + ? - f v + - fa v + . vs cap s r + - ds v . vdd cap dc v in r figure 28. application circuit transformer structure as mentioned in the constant voltage output regulation section, the psr controller incorporates a proprietary control design to achieve cv/cc regulations. a correct sampling voltage of the auxiliary winding is critical to the cv/cc performance. therefore, the coupling of the auxiliary winding and the secondary winding should be precise. the suggested transformer structure is shown in figure 29 and figure 30. the coupling coefficient between the secondary winding and the auxiliary winding can be effectively improved by sloughing off the emi shielding between auxiliary winding and secondary winding. further effectiveness is achieved by increasing the coupling area through a well-paved the auxiliary winding on the top layer. n 1 n 2 n 3 e mi shielding p rimary winding auxiliary winding secondary winding vin ' mos s d rain 1 2 3 4 6 8 figure 29. transformer winding (3) auxiliary winding n (2) () secondary winding n insulated (1) primary winding n emi shielding e mi shielding 1 2 3 6 4 8 figure 30. recommended tr ansformer structure
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 13 effect of the vs pin capacitor a v s capacitor with 22~68pf placed closely between vs pin and the gnd pin is recommended. the capacitor is used to bypass switching induced noise and keep the accuracy of the sampled voltage. the value of the capacitor affects the load regulation and constant current performance. figure 31 illustrates the measured waveform on the vs pin with a different v s capacitor. if a higher value v s capacitor is used, the charging time becomes longer and the sampled voltage is higher than the actual value. figure 32 shows the effect on the sampled voltage with a different v s capacitor. figure 33 shows a measured vs pin waveform at a no-load condition. as illustrated, the feedback voltage is too narrow. additionally, a large v s capacitor causes the inaccurate sampling of the voltage; resulting in the rising of the output voltage. figure 24 shows the influence of the v s capacitor on the v-i curve. figure 31. measured waveform with different v s capacitor s ampling voltage higher vs cap lower vs cap vs pin waveform - no load s ampling voltage figure 32. effect on sampling voltage with different v s capacitor no-load vs gate comv vf no-load vs gate comv vf figure 33. measured vs pin waveform at no load o v o i . lower vs cap . higher vs cap figure 34. comparison of v-i curve with different v s capacitor effect of v dd and snubber capacitors v dd voltage and snubber capacitors are related to the feedback signal inaccuracy and cause output voltage to rise at no-load condition. if the v dd capacitor is not big enough, the decreasing pwm frequency at no-load condition causes v dd voltage to drop quickly. in such a condition, the feedback signal is dominated by the v dd voltage, but not the secondary output voltage. to avoid this, it is recommended the v dd capacitor value be larger than 4.7f(6.8~10f). on the other hand, the value of the snubber capacitor also affects the output voltage performance. when the moseft is turned off, the polarity of the transformer primary side inductor is reversed and the energy stored in the transformer inductor is delivered to the s econdary to supply load current. in the meantime, if the output voltage is higher than the voltage on the secondary winding (v sec ), the output diode is still reversed. the resulting voltage v pri is then applied to the primary inductor, l p , which charges the snubber capacitor. the charge time influences the feedback voltage signal on the auxiliary winding. it is recommended that the snubber capacitor remain under 472pf(332~102pf).
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 14 vin - f v + - fa v + + - vaux + - vpri sec - v + ::1 ap nn vs 1 r 2 r 100 sgp vdd o v + ? . dd vcap . vs cap a r sec o vv > figure 35. v dd and snubber capacitors effect on output voltage reducing no-load output voltage with a ?dummy? load at no-load and very light load conditions, due to the very low pwm frequency caused by feedback signal deviations and output voltage rises, especially at low-line input voltage condition. increasing the addition of a dummy load can fix this problem. figure 36 shows the effect of a higher and lower dummy load on the v-i curve. the level of the dummy load is suggested at about 25~ 100mw. o v o i , , dd higher snubber cap lower v cap dummy load , , dd lower snubber cap higher v cap dummy load figure 36. dummy load effect on output characteristic
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 15 pcb layout considerations high-frequency switching current / voltage make pcb layout a very important design issue. good pcb layout minimizes excessive emi and helps the power supply survive during surge/esd tests. general guidelines the numbers in the following guidelines refer to figure 37. to improve emi performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors c1 an d c2 first, then to the switching circuits. the high-frequency current loop is in c2 ? transformer ? mosfet ? r7 ? c2 . the area enclosed by this current loop should be as small as possible. keep the traces (especially 4 1 ) short, direct, and wide. high voltage traces related to the drain of mosfet and rcd snubber should be kept far way from control circuits to prevent unnecessary interference. if a heatsink is used for the mosfet, connect this heatsink to a ground. as indicated by 3 , the ground of the control circuits should be connected first, then to other circuitry. as indicated by 2 , the area enclosed by the transformer aux winding, d1 and c3 , should also be kept small. place c3 close to the psr controller for good decoupling. suggestion for the ground connections gnd 3 2 4 1 : may make it possible to avoid common impedance interference for the sense signal. regarding the esd discharge path, the charges go from secondary through the transformer stray capacitance to gnd 2 first. then the charges go from gnd 2 to gnd 1 and back to the mains. it should be noted that control circuits should not be placed on the discharge path. 5 should a point-discharge route to bypass the static electricity energy. as shown in figure 38, it is suggested to map out this discharge route. start in secondary gnd to the positive terminal of c2 , then to front terminal of bridge rectifier. if this discharge route is connected to the primary gnd, it should be connected to the negative terminal of c2 (gnd1) directly. however, the creepage distance between these two pointed ends should be long enough to satisfy the requirements of applicable standards. comi comv sgnd vdd vs cs gate pgnd psr controller 1 2 3 4 5 6 7 8 bd1 c1 c2 l1 r1 d1 r2 c3 r3 r4 c5 d3 r5 r6 r7 d4 c6 r8 c7 r9 r10 c8 t1 u1 r13 4 2 3 1 5 5 figure 37. layout consideration
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 16 pcb layout considerations (continued) figure 38. pcb layout example (5v/1a, 5w power board)
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 17 reference circuits comi comv sgnd vdd vs cs gate pgnd 1 2 3 4 5 6 7 8 bd1 c1 c2 l1 r1 d1 r2 c3 r3 r4 c4 r5 r6 r7 d3 c5 r8 c6 r9 r10 c7 d4 c8 r11 c9 c10 l2 r12 t1 u1 r13 figure 39. application circuit fan100 (5v/1a) bom list symbol component symbol component r1 resistor 1.5m 1/2w d4 diode 5a/60v sb560 r2 resistor 4.7 c1 electrolytic capacitor 1f/400v r3 resistor 115k 1% c2 electrolytic capacitor 10f/400v r4 resistor 18k 1% c3 electrolytic capacitor 10f/50v r5 resistor 47 c4 mlcc x7r 22pf r6 resistor 100 c5 snubber capacitor 472pf/1kv r7 resistor 1.4 1/2w 1% c6 mlcc x7r 683pf r8 resistor 100k 1/2w c7 mlcc x7r 103pf r9 resistor 200k c8 mlcc 102pf/100v r10 resistor 30k c9 electrolytic capacitor 560uf/10v l-esr r11 resistor 47 c10 electrolytic capacitor 330f/10v l-esr r12 resistor 510 l1 inductor 1mh r13 wirewound resistor 18 l2 inductor 5h bd1 rectifier diode 1n4007 *4 q1 fairchild 2a/600v 2n60 to-251 d1 diode 1a/200v fr103 u1 fan100 d3 diode 1a/1000v 1n4007 tr1 ee-16 lm=1.5mh pri:sec:aux=135:10:33
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 18 reference circuits (continued) comi comv gnd vdd vs cs drain n.c. 1 7 3 4 5 2 6 8 bd1 c1 c2 l1 r1 d1 c3 r2 r3 c4 r4 d3 c5 r5 c6 r6 r7 c7 d4 c8 r8 c9 c10 l2 r9 t1 u1 r10 figure 40. application circuit fsez1016a (fan100 + mosfet) (5v/1a) bom list symbol component symbol component r1 resistor 1.5m c1 electrolytic capacitor 1f/400v r2 resistor 127k 1% c2 electrolytic capacitor 10f/400v r3 resistor 20k 1% c3 electrolytic capacitor 10f/50v r4 resistor 1.36 1/2w 1% c4 mlcc x7r 47pf r5 resistor 100k 1/2w c5 snubber capacitor 472pf/1kv r6 resistor 200k c6 mlcc x7r 683pf r7 resistor 39k c7 mlcc x7r 103pf r8 resistor 47 c8 mlcc 102pf/100v r9 resistor 510 c9 electrolytic capacitor 560f/10v r10 wirewound resistor 18 c10 electrolytic capacitor 330f/10v bd1 rectifier diode 1n4007 *4 l1 inductor 1mh d1 diode 1a/200v fr103 l2 inductor 5h d3 diode 1a/1000v 1n4007 u1 fsez1016a d4 diode 5a/60v sb560 tr1 ee-16 lm=1.5mh pri:sec:aux=135:10:33
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 19 reference circuits (continued) comi comv gnd vdd vs cs gate comr 1 2 3 4 5 6 7 8 bd1 c1 c2 l1 r1 d1 r2 c3 r3 r4 c5 r5 r6 r7 d3 c6 r8 c7 r9 r10 c8 d4 c9 r11 c10 c11 l2 r12 t1 u1 r13 c4 q1 figure 41. application circuit fan102 (5v/1a) bom list symbol component symbol component symbol component r1 resistor 1.5m 1/2 w d3 diode 1a/1000v 1n4007 q1 1a/600v 1n60 to-251 r2 resistor 82k 1% d4 diode 5a/60v sb560 tr1 ee-16 lm=1.5mh pri:sec:aux=135:10:33 r3 resistor 110k 1% c1 electrolytic capacitor 1f/400v u1 fan102 r4 resistor 18k 1% c2 electrolytic capacitor 10f/400v r5 resistor 47 c3 electrolytic capacitor 10f/50v r6 resistor 100 c4 mlcc 104pf r7 resistor 1.4 1/4w 1% c5 mlcc x7r 22pf r8 resistor 100k 1/2w c6 snubber capacitor 472pf/1kv r9 resistor 200k c7 mlcc x7r 683pf r10 resistor 47k c8 mlcc x7r 103pf r11 resistor 20 c9 mlcc 102pf/100v r12 resistor 510 c10 electrolytic capacitor 560f/10v l-esr r13 wirewound resistor 18 c11 electrolytic capacitor 330f/10v l-esr bd1 rectifier diode 1n4007 *4 l1 inductor 1mh 1/2w d1 diode 1a/200v fr103 l2 inductor 5h
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 20 reference circuits (continued) comi comv gnd vdd vs cs drain comr 1 2 3 4 5 7 6 8 bd1 c1 c2 l1 r1 d1 c3 r2 r3 c4 r4 d3 c5 r5 c6 r6 r7 c7 d4 c8 r8 c9 c10 l2 r9 t1 u1 r10 r11 c11 figure 42. application circuit FSEZ1216 (5v/1a) bom list symbol component symbol component symbol component r1 resistor 1.5m d4 diode 5a/60v sb560 u1 FSEZ1216 r2 resistor 110k 1% c1 electrolytic capacitor 1f/400v tr1 ee-16 lm=1.5mh pri:sec:aux=135:10:33 r3 resistor 18k 1% c2 electrolytic capacitor 10f/400v r4 resistor 1.4 1/2w 1% c3 electrolytic capacitor 10f/50v r5 resistor 100k 1/2w c4 mlcc x7r 47pf r6 resistor 200k c5 snubber capacitor 472pf/1kv r7 resistor 47k c6 mlcc x7r 683pf r8 resistor 47 c7 mlcc x7r 103pf r9 resistor 510 c8 mlcc 102pf/100v r10 wirewound resistor 18 c9 electrolytic capacitor 560f/10v r11 resistor 82k 1% c10 electrolytic capacitor 330f/10v bd1 rectifier diode 1n4007 *4 c11 mlcc x7r 104pf d1 diode 1a/200v fr103 l1 inductor 1mh d3 diode 1a/1000v 1n4007 l2 inductor 5h
an-6067 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 1/26/10 21 related datasheets fan100 ? primary-side regulation pwm controller fan102 ? primary-side regulation pwm controller fsez1016a ? primary-side regulation pwm with integrated power mosfet FSEZ1216 ? primary-side regulation pwm with integrated power mosfet disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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